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CXA2069Q
S2-Compatible 7-Input 3-Output Audio/Video Switch
Description The CXA2069Q is a 7-input, 3-output audio/video switch featuring I2C bus compatibility for TVs. This IC has input pins that are compatible with S2 protocol. Features * 4 inputs that are compatible with S2 protocol * Serial control with I2C bus * 7 inputs, 3 outputs * The desired inputs can be selected independently for each of the 3 outputs * Wide band video amplifier (20 MHz, -3 dB) * Y/C MIX circuit * Slave address can be changed (90H/92H) * Audio muting from external pin * High impedance maintained by I2C bus lines (SDA, SCL) even when power is OFF * Wide audio dynamic range (3 Vrms typ.) Applications Audio/video switch featuring I2C bus compatibility for TVs Structure Bipolar silicon monolithic IC 64 pin QFP (Plastic)
Absolute Maximum Ratings (Ta=25 C) * Supply voltage VCC 12 * Operating temperature Topr -20 to +75 * Storage temperature Tstg -65 to +150 * Allowable power dissipation PD 1300 Operating Conditions Supply voltage
V C C mW
90.5
V
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
--1--
E96Y05B81
CXA2069Q
Block Diagram
TV V1 V2 V3 V4 V5 V6 63
1 8
15 22 30 6dB 60 6dB
53
VOUT1
49 56 55
YIN1 YOUT1 TRAP1
58 6dB 51 Y1 Y2 Y3 Y4
COUT1 CIN1
3
10 17 24 6dB 46 TRAP2 6dB 44 V/YOUT2
47 6dB
COUT2
C1 C2 C3 C4
5
12 19 26 6dB 6dB
41
VOUT3
39
YOUT3
37 6dB BIAS 6dB 57 50 42 LTV LV1 LV2 LV3 LV4 LV5 LV6 RTV RV1 RV2 RV3 RV4 RV5 RV6 62 35 52 54 0dB 6dB 43 45 29 59 64 0dB 38 40
COUT3 VGND BIAS VCC AGND LOUT1 ROUT1 LOUT2 ROUT2 LOUT3 ROUT3
2 9
16 23
4
11 18 25 31 61 6dB Logic 6dB 6dB 36 33 34 32 DC OUT SCL SDA ADR S-1 S-2 S-3 S-4 S2-1 S2-2 S2-3 S2-4 MUTE
7
14 21 28
6
13
Audio system is attenuated by 6dB at input, and a total gain is 0dB (LOUT1 and ROUT1 can be changed to -6dB).
20 6dB 27 48
--2--
Pin Configuration
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VCC
CIN1
MUTE
TRAP2
LOUT2
ROUT2
LOUT3
VOUT3
ROUT3
COUT2
YOUT3
COUT3
AGND
V/YOUT2
DC OUT
52 ADR RV5 31 V5 30 LV5 29 S-4 28 S2-4 27
BIAS
YIN1
SDA SCL
32 C4 26 RV4 25 Y4 24 LV4 23 V4 22 S-3 21 S2-3 20 19
LOUT1
53 VOUT1
54 ROUT1
55 TRAP1
56 YOUT1
57 VGND
S-1
RV1
V1
S2-1
LV2
C2
V3
Y1
V2
RV2
S-2
Y3
RV3 Y2
11 12 13 14 15 16
C1
LV1
1
2
3
4
5
6
7
8
9
10
S2-2
LV3
17
18
C3
--3--
58 COUT1
CXA2069Q
59 LV6
60 V6
61 RV6
62 LTV
63 TV
64
RTV
CXA2069Q
CXA2069Q
Pin Description Pin No. 63 1 8 15 22 30 60 Symbol TV V1 V2 V3 V4 V5 V6 Pin voltage Equivalent circuit
VCC 63 22 150 30 60 3A
Description
1
4.0 V
8
15
Video signal inputs. Input composite video signals.
VCC
3
3 10 17 24 49
Y1 Y2 Y3 Y4 YIN1
10 150
4.0 V
17 24 49 3A
Y/C separation signal inputs. Input luminance signals. The YIN1 pin inputs the signal obtained by Y/C separating the VOUT1 pin output.
VCC
5
5 12 19 26 51
C1 C2 C3 C4 CIN1
12
20k
4.5 V
19 26 51 150 27k
Y/C separation signal inputs. Input chrominance signals. The CIN1 pin inputs the signal obtained by Y/C separating the VOUT1 pin output.
62
64 VCC
62, 2 9, 16 23, 29 59, 64 4, 11 18, 25 31, 61
LTV, LV1 LV2, LV3 LV4, LV5 LV6, RTV RV1, RV2 RV3, RV4 RV5, RV6
2 9
4
11 18 25 31 61 27k 15k 33k
4.5 V
16 23 29 59
Audio signal inputs.
VCC 250 VCC
53 41
VOUT1 VOUT3
3.9 V
53 41
30k 27k 23.5k
Video signal outputs. Output composite video signals.
--4--
CXA2069Q
Pin No.
Symbol
Pin voltage
Equivalent circuit
VCC VCC VCC
Description
VCC
44
V/YOUT2
3.8 V
44
Video signal output. Either composite video signal output or luminance signal output can be selected by I2C bus control.
VCC
VCC
VCC
VCC
56
YOUT1
3.3 V
56 39
Video signal outputs. Output luminance signals.
39
YOUT3
3.8 V
VCC
VCC
VCC
VCC
58 47 37
COUT1 COUT2 COUT3
58
4.5 V
47 37
Video signal outputs. Output chrominance signals.
VCC
VCC
52 43 38 54 45 40
LOUT1 LOUT2 LOUT3 ROUT1 ROUT2 ROUT3
54 45
52 56 43 38 20k 20k
4.5V
40
Audio signal outputs. Zo=50 (within DC 2 mA)
VCC
VCC
VCC
6
6 13 20 27
S2-1 S2-2 S2-3 S2-4
13
--
20 27
147
100k
Detects the S2-compatible DC superimposed onto the C signal. 4 : 3 video signal at 1.3 V or less 4 : 3 letter-box signal at 1.3 V or more to 2.5 V or less 16 : 9 picture squeezed signal at 2.5 V or more This pin is pulled down to GND by a 100 k resistor, so the 4 : 3 video signal is selected when open.
--5--
CXA2069Q
Pin No.
Symbol
Pin voltage
Equivalent circuit
Description Composite video/S selector. The detection results are written to the status register. S signal at 3.5 V or less Composite video signal at 3.5 V or more This pin is pulled up to 5 V by a 100 k resistor, so the composite video signal is selected when open.
5V VCC
VCC 50k
VCC
7 14 21 28
S-1 S-2 S-3 S-4
7
14
--
21 28
100k 50k
100k
VCC
147
72k
32
ADR
--
32 28k
Selects the slave address for the I2C bus. 90H at 1.5 V or less 92H at 2.5 V or more 90H when open.
VCC
4k
33
SCL
--
33
I2C bus signal input VILmax=1.5 V VIHmin=3.0 V
10.5k
VCC
4k
34
SDA
--
34
I2C bus signal input VILmax=1.5 V VIHmin=3.0 V VOLmax=0.4 V
--6--
CXA2069Q
Pin No.
Symbol
Pin voltage
Equivalent circuit
Description Outputs the S2-compatible DC superimposed onto the COUT3 output. The DC is superimposed by connecting this pin to the COUT3 output via a capacitor. Control is performed by the I2C bus. When 0 V is output, Q1 is ON and the impedance is 5 k. S2 protocol output impedance of 10 3 k is realized by attaching external resistance of 4.7 k. DC_OUT (bus) Output DC 0 4.5 V 1 0V 2 1.9 V 3 4.5 V
VCC
4k
1k Q1 28k
36
DC_OUT
--
36
VCC
55 46
TRAP1 TRAP2
100
3.8 V
55 46 1k
Connects trap circuit for subcarrier.
VCC
147
72k
48
MUTE
--
48 28k
Audio signal output mute. Mute OFF at 1.5 V or less Mute ON at 2.5 V or more Mute OFF when open.
VCC
VCC
VCC
20k
50
BIAS
4.5 V
147 50 20k
Internal reference bias (VCC/2). Connect to GND via a capacitor.
--7--
CXA2069Q
Electrical Characteristics Item Current consumption Symbol ICC Conditions No signal, no load Min. 40
(Ta=25 C VCC=9 V) Typ. 55 Max. 72 Unit mA
Video system (Measurement circuit ; Fig. 1) Gain
Frequency response characteristics Frequency response characteristics (Y/C mix)
GVv FBWv1 FBWv2 Ddv Vctv
f=100 kHz, 0.3 Vp-p input f=100 kHz, input frequency where output amplitude is -3 dB with 0.3 Vp-p output serving as 0 dB f=100 kHz, maximum with distortion < 1.0 % f=4.43 MHz, 1 Vp-p input
5.9 15 10 1.4 --
6.4 20 15 -- --
6.9
dB MHz
-- -- -50
MHz Vp-p dB
Input dynamic range Cross talk
Audio system (Measurement circuits ; Fig. 2 to Fig. 5) Gain Frequency response characteristics Total harmonic distortion Input dynamic range Cross talk Ripple rejection ratio Output DC offset Residual noise S/N ratio GVA f=1 kHz, 1 Vp-p input, 5.7 k resistor inserted to input f=1 kHz, input frequency where output amplitude is -3 dB with 1 Vp-p output serving as 0 dB f=1 kHz, 2.2 Vp-p input, where 400 Hz HPF+80 kHz LPF are inserted f=1 kHz, maximum with distortion < 0.3 % f=1 kHz, 1 Vp-p input f=100 Hz, 0.3 Vp-p applied to VCC Offset voltage between input and output When 400 Hz HPF+30 kHz LPF are inserted f=1 kHz, 1 Vrms input fCL=400 Hz, fCH=30kHz -1 0 1 dB
FBWA
50
--
--
kHz
THD DdA VctA VctA Voff VNA S/N
-- 2.8 -- -- -30 0
0.03 3.0 -90 -55 -- 20 -100
0.05 -- -80 -40 30 30 -90
% Vrms dB dB mV Vrms dB
--8--
CXA2069Q
Logic system Item Symbol Conditions Min. 3.0 0 With SDA 3 mA current supplied VIH=4.5V VIL=0.4V 0 0 0 0 4.7 4.0 4.7 4.0 4.7 300 250 -- -- 4.7 Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 5.0 1.5 0.4 10 10 100 -- -- -- -- -- -- -- 1 300 -- Unit V V V A A kHz s s s s s ns ns s ns s
High level VIH input voltage Low level VIL input voltage Low level VOL output voltage High level IIH input current Low level IIL input current Maximum clock fSCL frequency Minimum waiting time tBUF for data change Minimum waiting time tHD;STA for data transfer start Low level clock tLOW pulse width High level clock tHIGH pulse width Minimum waiting time tSU;STA for start preparation Minimum data tHD;DAT hold time Minimum data tSU;DAT preparation time Rise time Fall time tR tF
Minimum waiting time tSU;STO for stop preparation
--9--
CXA2069Q
Measurement point
V
10k 10k 10k 10k 10k 10k 75 75
10
10k
10k
10k
22
0.1
0.47
1k
con
10
10
10
38 37
10
10
10
51
50
49
48
47
46
45
10
44
43
42
41
40
39
10
10
36
35
34
33
ROUT2
MUTE
ROUT3
COUT3
CIN1
TRAP2
LOUT2
VOUT3
LOUT3
AGND
YIN1
SDA
V/YOUT2
COUT2
10k 10k 10k
10 10 10
52
DC OUT
BIAS
YOUT3
SCL
ADR
VCC
LOUT1
32 1 0.47 1 600 75 600
53 VOUT1 54 ROUT1 55 TRAP1
RV5 31 V5 30 LV5 29 S-4 28 S2-4 27
10k
10 56 YOUT1 57 VGND
10k 600
10 1
58 COUT1 59 LV6 60 V6 61 RV6 62 LTV 63 TV
CXA2069Q
C4 26 RV4 25 Y4 24 LV4 23 V4 22 S-3 21
0.1 1 0.47 1 0.47
75 600 75 600 75
75 0.47 600 600 1 1
75 0.47 600 1
S2-1
S2-2
RV1
RV2
LV2
LV1
LV3
S-1
S-2
C2
V3
RV3
64
RTV
S2-3
20
C1
V2
1
0.47 1
2
0.47
3
1
4
0.1
5
6
7
0.47
8
1
9
0.47
10
Y2
11
12
13
14
15
16
17
18
19
0.47
0.47
0.1
600
600
600
600
600
600
75
75
75
75
75
75
75
Input signal
Signal is input from one of the following pins: 1, 3, 5, 8, 10, 12, 15, 17, 19, 22, 24, 26, 30, 60 and 63. Output signal is measured from one of the following pins: 37, 39, 41, 44, 47, 53, 56 and 58.
Fig. 1 Video system (gain, frequency response characteristics, input dynamic range, cross talk) measurement circuit
Measurement point
75
75
0.1
1
1
1
10k
10k
10k
10k
10k
10k
75
75
10
10k
10k
10k
22
C3
V1
Y1
Y3
V
0.1
0.47
1k
con 10 10 10 10 38 LOUT3 37 COUT3 10 10 10 10 10 36 DC OUT
51 CIN1 10k 10k 10k 10 10 10 52
50 BIAS
49 YIN1
48 MUTE
47 COUT2
46 TRAP2
45 ROUT2
44 V/YOUT2
43 LOUT2
42 VCC
41 VOUT3
40 ROUT3
39 YOUT3
35 AGND
34 SDA
33 SCL ADR 32 5.7k 1 0.47 5.7k 1 75 600 600
LOUT1
53 VOUT1 54 ROUT1 55 TRAP1
RV5 31 V5 30 LV5 29 S-4 28 S2-4 27
10k
10 56 YOUT1 57 VGND
10k 600
10
58 COUT1 59 LV6 60 V6 61 RV6 62 LTV
CXA2069Q
C4 26 RV4 25 Y4 24 LV4 23 V4 22 S-3 21
0.1 5.7k 1 0.47 5.7k 1 0.47
75 600 75 600 75
1 5.7k 75 0.47
600 600
1 5.7k 1 5.7k
S2-1
S2-2
RV1
RV2
LV2
LV1
LV3
S-2
C2
V1
V3
RV3
S-1
75 0.47 63 TV 1 5.7k 600 RTV 64
S2-3 C3 19 0.1 75
20
C1
Y1
V2
1
1 5.7k 0.47
2
0.47
3
1 5.7k
4
0.1
5
6
7
0.47
8
1 5.7k
9
0.47
10
Y2
11 1 5.7k 0.1
12
13
14 0.47
15 1 5.7k
16 0.47
17 1 5.7k 600
Y3 75
18
75
75
75
75
75
600
600
600
600
75
75 600
Input signal
Signal is input from one of the following pins: 2, 4, 9, 11, 16, 18, 23, 25, 29, 31, 59, 61, 62 and 64. Output signal is measured from one of the following pins: 38, 40, 43, 45, 52 and 54.
Fig. 2 Audio system (gain, frequency response characteristics, total harmonic distortion, input dynamic range, cross talk) measurement circuit
--10--
CXA2069Q
Measurement point
100Hz, 0.3Vp-p
V
10k 10k 10k 10k 10k
10k
10k
75
75
10
10k
10k
0.1
0.47
1k
con
10
10
10
38 37
10
10
10
51
50
49
48
47
46
45
10
44
43
42
41
40
39
10
10
36
35
34
33
ROUT2
MUTE
ROUT3
COUT3
CIN1
TRAP2
LOUT2
VOUT3
LOUT3
AGND
YIN1
SDA
V/YOUT2
COUT2
10k 10k 10k
10 52 10 10
DC OUT
BIAS
YOUT3
SCL
ADR
VCC
LOUT1
32 1 0.47 1 600 75 600
53 VOUT1 54 ROUT1 55 TRAP1
RV5 31 V5 30 LV5 29 S-4 28 S2-4 27
10k
10 56 YOUT1 57 VGND
10k 600
10 58 COUT1 1 59 LV6 60 V6 61 RV6 62 LTV 63 TV
CXA2069Q
C4 26 RV4 25 Y4 24 LV4 23 V4 22 S-3 21
0.1 1 0.47 1 0.47
75 600 75 600 75
75 0.47 600 600 1 1
75 0.47 600 1
S2-1
S2-2
RV1
RV2
LV2
LV1
LV3
S-1
S-2
C2
V3
RV3
64
RTV
S2-3
20
C1
V2
1
0.47 1
2
0.47
3
1
4
0.1
5
6
7
0.47
8
1
9
0.47
10
Y2
11
12
13
14
15
16
17
18
19
0.47
0.47
0.1
600
600
600
600
600
600
75
75
75
75
75
75
75
A f=100Hz, 0.3Vp-p signal is applied to Vcc and the output signals from Pins 38, 40, 43, 45, 52 and 54 are measured.
Fig. 3 Audio system (ripple rejection ratio) measurement circuit
Measurement point
75
75
0.1
1
1
1
C3
V1
Y1
Y3
V
10k 10k 10k 10k 10k 10k 75 75
10
10k
10k
10k
22
0.1
0.47
1k
con
10
10
10
10
38 37
10
10
51
50
49
48
47
46
45
10
44
43
42
41
40
39
10
10
36
35
34
33
ROUT2
MUTE
ROUT3
COUT3
CIN1
TRAP2
LOUT2
VOUT3
LOUT3
AGND
YIN1
SDA
V/YOUT2
COUT2
10k 10k 10k
10 52 10 10
DC OUT
BIAS
YOUT3
SCL
ADR
VCC
LOUT1
32 5.7k 1 0.47 5.7k 1 75 600 600
53 VOUT1 54 ROUT1 55 TRAP1
RV5 31 V5 30 LV5 29 S-4 28 S2-4 27
10k
10 56 YOUT1 57 VGND
10k 600
10 58 COUT1 59 LV6 60 V6 61 RV6 62 LTV
CXA2069Q
C4 26 RV4 25 Y4 24 LV4 23 V4 22 S-3 21
0.1 5.7k 1 0.47 5.7k 1 0.47
75 600 75 600 75
1 5.7k 75 0.47
600 600
1 5.7k 1 5.7k
S2-1
S2-2
600
RV1
RV2
LV2
LV1
LV3
S-1
S-2
C2
V3
RV3
75 0.47 63 TV 1 5.7k RTV 64
S2-3
20
C1
V2
1
1 5.7k 0.47
2
0.47
3
1 5.7k
4
0.1
5
6
7
0.47
8
1 5.7k
9
0.47
10
Y2
11
12
13
14
15
16
17
18
19
1 5.7k
1 5.7k
1 5.7k
0.47
0.47
0.1
75
75
75
75
75
75
75
75
600
600
600
600
V
Measurement point
Fig. 4 Audio system (output DC offset voltage) measurement circuit --11--
600
600
75
0.1
C3
V1
Y1
Y3
CXA2069Q
40dB
Measurement point
V
10k 10k 10k 10k 10k 10k 75 10k 10k 75 10k
10 4.5V 22
0.1
0.47
1k
con
10
10
10
10
38 37
10
10
51
50
49
48
47
46
45
10
44
43
42
41
40
39
10
10
36
35
34
33
ROUT2
MUTE
ROUT3
COUT3
CIN1
TRAP2
LOUT2
VOUT3
LOUT3
AGND
YIN1
SDA
V/YOUT2
COUT2
10k 10k 10k
10 10 10
52
DC OUT
BIAS
YOUT3
SCL
ADR
VCC
LOUT1
32 1 0.47 1 600 75 600
53 VOUT1 54 ROUT1 55 TRAP1
RV5 31 V5 30 LV5 29 S-4 28 S2-4 27
10k
10 56 YOUT1 57 VGND
10k 600
10 1
58 COUT1 59 LV6 60 V6 61 RV6 62 LTV 63 TV
CXA2069Q
C4 26 RV4 25 Y4 24 LV4 23 V4 22 S-3 21
0.1 1 0.47 1 0.47
75 600 75 600 75
75 0.47 600 600 1 1
75 0.47 600 1
S2-1
S2-2
RV1
RV2
LV2
LV1
LV3
S-1
S-2
C2
V3
RV3
64
RTV
S2-3
20
C1
V2
1
0.47 1
2
0.47
3
1
4
0.1
5
6
7
0.47
8
1
9
0.47
10
Y2
11
12
13
14
15
16
17
18
19
0.47
0.47
0.1
600
600
600
600
600
600
75
75
75
75
75
75
75
Fig. 5 Audio system (residual noise) measurement circuit
75
--12--
75
0.1
1
1
1
C3
V1
Y1
Y3
Application Circuit
VIDEO 2 output
VIDEO 3 output
con
51
50
49
48
47
46
620 180 10p
0.1 45 44 43 42 41 40 39 38 37 36 35 34 33
0.47
1k
0.1
VCC
220
220
COMB FILTER 10 22
* Depending on the output bias of the comb filters, pay attention to the polarities of the capacitors since the bias at Pins 49 and 51 is approximately 3.1V and 4.5V, respectively. * Connect Pin 32 to VCC when setting the slave address of the IC to 92H. * The audio output can be muted by setting Pin 48 to 3.5V or more. * The TRAPs (Pins 46 and 55) are of 3.58MHz subcarrier. * The output impedance of the audio signal source must be 4.7k. * Pay attention to the polarities of the capacitors since each output of video system and audio system has optional bias, respectively.
CIN1
BIAS
YIN1
SDA SCL
MUTE
TRAP2
LOUT2
ROUT2
LOUT3
VOUT3
ROUT3
COUT2
YOUT3
COUT3
AGND
52 ADR 1 0.47 V5 30 1 LV5 29 S-4 28 S2-4 27 0.1 75 1 RV4 25 0.47 Y4 24 1 LV4 23 0.47 V4 22 S-3 21 S2-3 1 RV5 31
53 VOUT1
10p 180 620
54 ROUT1
VIDEO 1 output
56 YOUT1
57 VGND
1
58 COUT1
CXA2069Q
C4 26
VIDEO 6 input
1
62 LTV
0.47
63 TV
TV input
1
S-1
RV1
V1
S2-1
LV2
C2
V3
Y1
V2
RV2
S-2
Y3
RV3
64
RTV
20 15 16
C1
LV1
1
1 1 1 0.1 0.47 0.47 0.1
2
3
4
5
6
7
8
9
10
Y2
11
12
13
S2-2
14
LV3
17
18
19
1
1
1
0.47
0.47
75
75
0.47
0.47
0.1
C3
75
75
75
75
75
75
470k
470k
75
470k
470k
1
470k
470k
VIDEO 1 input
VIDEO 2 input
1
VIDEO 3 input
CXA2069Q
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
1
VIDEO 4 input
--13--
0.47
59 LV6
1
60 V6
61 RV6
VIDEO 5 input
55 TRAP1
V/YOUT2
DC OUT
LOUT1
32
Drive this input with low impedance to prevent cross talk for this pin.
CXA2069Q
I2C BUS Control Signal
34
SDA tBUF
33
SCL tR tF
tHD;STA tLOW P S
tHD;DAT
tHIGH
tSU;DAT
tSU;STA S
tSU;STO P
Fig. 6 I2C BUS Control Signal Timing Chart
Description of Operation The CXA2069Q is a TV I2C bus-compatible AV switch IC. The video system and the stereo audio system both have 7 inputs and 3 outputs each. 4 of the 7 video system inputs support S2 and S protocols. The desired inputs can be independently assigned to each output (in the audio system, the left and right channels are processed as one unit) by I2C bus control. However, the same input is assigned to both the video and audio system output 3. I2C BUS Registers 1) I2C BUS The I2C bus (inter-IC bus) is an inter-IC bus system developed by Philips. Two lines (SDA-serial data, SCL-serial clock) provide control over start, stop, data transfer, synchronization, and collision avoidance. The IC outputs are either open collector or open drain, forming a bus line in the wired OR format.
SDA
A
A
MSB SCL S 1 2 3 4 5 6 7
LSB
MSB
LSB
P 8 9 1 2 9
S : Start condition ; SDA is set "Low" when SCL is "High" P : Stop condition ; SDA is set "High" when SCL is "High" A : Acknowledge ; signal sent from the slave Data is transmitted by MSB-first. One data unit consists of 8 bits, to which the acknowledge signal, which indicates that the data has been accepted by the slave, is attached at the end. Normally, the slave1 IC receives data at the rising edge of SCL and the master2 IC changes data at the falling edge of SCL. 1 2 Slave : An IC that is placed under the control of the master. In a normal system, all devices excluding the central microcomputer are slaves. Master : A central microcomputer or other controlling IC. --14--
CXA2069Q
2) Control Registers The CXA2069Q control is exercised by writing 3-byte data into the three 8-bit control registers which control the output selector circuits for the 3 outputs. S Slave address A DATA1 A DATA2 A DATA3 AP S ; Start condition A ; Acknowledge P ; Stop condition O Control register structure (DATA1 to DATA3) * All registers are set to "0" during IC power on. * "" indicates undefined. b7 b6 b5 b4 Slave add. DATA1 DATA2 DATA3 1 0 A-GAIN S/COMP1 V/YOUT S/COMP2 S/COMP3 0 1 V-IN1 V-IN2 AV-IN3
b3 0
b2 0
b1 ADR A-IN1 A-IN2 DC OUT
b0 R/W
R/W (1) : Read/write mode 0 : Control data write 1 : Status register read ADR (1) : This bit sets the slave address set by the address pin. 0 : 90H 1 : 92H A-GAIN (1) : LOUT1/ROUT1 output gain selector 0 : 0 dB output 1 : -6 dB output S/COMP1 to S/COMP3 (1 each) : S terminal input/composite signal input selectors By setting S/COMP1 to "0", when composite signal input is selected, YOUT1/COUT1 output the inputs from YIN1/CIN1 during video 1 output. 0 : Composite signal inputs (TV, V1 to V6 inputs) 1 : S terminal inputs (Y1/C1 to Y4/C4 inputs) V/YOUT (1) : This bit selects the output to Pin 44 (V/YOUT2). 0 : VOUT (composite signal) output 1 : YOUT (luminance signal) output V-IN1 to V-IN2 (3 each) : These bits select the input signals output to each video output. V-IN1 corresponds to the VOUT1 and YOUT1/COUT1 outputs, and V-IN2 to the VOUT2 and YOUT2/COUT2 outputs. 0 : Mute 4 : Selects the V3 and Y3/C3 inputs 1 : Selects the TV input 5 : Selects the V4 and Y4/C4 inputs 2 : Selects the V1 and Y1/C1 inputs 6 : Selects the V5 input 3 : Selects the V2 and Y2/C2 inputs 7 : Selects the V6 input --15--
CXA2069Q
A-IN1 to A-IN2 (3 each) : These bits select the input signals output to each audio output. A-IN1 corresponds to the LOUT1/ROUT1 outputs, and A-IN2 to the LOUT2/ROUT2 outputs. 0 : Mute 4 : Selects the LV3/RV3 inputs 1 : Selects the LTV/RTV inputs 5 : Selects the LV4/RV4 inputs 2 : Selects the LV1/RV1 inputs 6 : Selects the LV5/RV5 inputs 3 : Selects the LV2/RV2 inputs 7 : Selects the LV6/RV6 inputs AV-IN3 (3) : This bit selects the input signals output to output 3. Both the video output and the audio output are selected at the same time only for AV-IN3. 0 : Mute 4 : Selects the V3, Y3/C3 and LV3/RV3 inputs 1 : Selects the TV and LTV/RTV inputs 5 : Selects the V4, Y4/C4 and LV4/RV4 inputs 2 : Selects the V1, Y1/C1 and LV1/RV1 inputs 6 : Selects the V5 and LV5/RV5 inputs 3 : Selects the V2, Y2/C2 and LV2/RV2 inputs 7 : Selects the V6 and LV6/RV6 inputs DC OUT (2) : These bits set the DC voltage output from Pin 35 (DC OUT). 0 : 4.5 V 1:0V 2 : 1.9 V 3 : 4.5 V
3) Status Registers * When reading two bytes S Slave address A * When reading one byte S Slave address A S; A; NA ; P; Start condition Acknowledge No acknowledge Stop condition
DATA1 DATA1
A NA P
DATA2
NA P
When communication is to be terminated in the status register reading mode, the "no-acknowledge" signal is needed to assure that the master does not issue the acknowledge signal to the slave. It is possible to read only DATA1 of the status register by sending the no-acknowledge signal after DATA1. O Status register structure (DATA1 to DATA2) b7 b6 b5 Slave add. DATA1 DATA2 1 S1SEL S1SEL 0 S2SEL S2SEL 0 S3SEL S3SEL
b4 1 S4SEL S4SEL
b3 0 S-C1 S-C3
b2 0
b1 ADR S-C2 S-C4
b0 1
--16--
CXA2069Q
S1SEL to S4SEL (1 each) : S-1 to S-4 pin status 0 ; S-1 to S-4 pins are not grounded. 1 ; S-1 to S-4 pins are grounded. S1SEL to S4SEL are actually determined by comparing the S-1 to S-4 pin DC voltages with 3.5 V.
S-1 to S-4 pin DC voltage S1SEL to S4SEL 3.5 V or more 0 3.5 V or less 1
S-C1, S-C2, S-C3, S-C4 (2 each) : S2-1, S2-2, S2-3 and S2-4 pin status 0 ; 4 : 3 video signal S2-1 to S2-4 pin DC voltage 1 ; 4 : 3 letter-box signal 1.3 V or less 2 ; 16 : 9 video squeezed signal 1.3 V or more to 2.5 V or less 3 ; No signal 2.5 V or more S-C1 to S-C4 are actually determined by S-1 to S-4 OPEN comparing the S2-1 to S2-4 pin DC voltages with two threshold. However, when the S-1 to S-4 pins are open, the outputs are fixed to "3".
S-C1 to S-C4 0 1 2 3
4) Power-on Reset The CXA2069Q has an internal power-on reset function that sets each control register to "0" during IC power ON. The power-on reset VTH has hysteresis.
Power-on reset released
Power-on reset
4.5V
5.6V
VCC
--17--
CXA2069Q
Video system frequency response characteristics 8
Video system input/output gain [dB]
6 Y1/C1 to Y4/C4 VOUT1 to VOUT3
TV, V1 to V6 VOUT1 to VOUT3 Y1 to Y4 YOUT1 to YOUT3 C1 to C4 COUT1 to COUT3
4
2
0
-2 100k
1M Frequency [Hz]
10M
100M
Audio system frequency response characteristics 2
Audio system input/output gain [dB]
L/RTV, L/R1 to L/R6 LOUT1 (0dB) L/RTV, L/R1 to L/R6 LOUT2 to LOUT3
0
-2
-4 L/RTV, L/R1 to L/R6 LOUT1 (-6dB) -6
-8
1k
10k 100k Frequency [Hz]
1M
Audio system distortion vs. Input amplitude 10
f=1kHz 400Hz HPF, 80kHz LPF
Total harmonic distortion [%]
1
0.1 LOUT1 output (0dB gain)
0.01
LOUT2 and LOUT 3 outputs
0.002 0 1 2 Input amplitude [Vrms] 3 4
--18--
CXA2069Q
Package Outline
Unit : mm
64PIN QFP(PLASTIC)
23.9 0.4 + 0.4 20.0 - 0.1
51 33
+ 0.1 0.15 - 0.05 0.15
52
32
17.9 0.4
+ 0.4 14.0 - 0.1
64
20
+ 0.2 0.1 - 0.05
1 1.0 + 0.15 0.4 - 0.1
+ 0.35 2.75 - 0.15 0.2 M 0 to10
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-64P-L01 QFP064-P-1420 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 1.5g
--19--
0.8 0.2
19
16.3

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